The present invention relates to a memory access system and, more particularly, to a memory access system for translating a logical address supplied from a processor into a real address and accessing a memory by using this real address.
In a memory access system of a paging system, for example, an address consists of page and intra-page addresses which are respectively represented by the upper and lower bit portions. Each real intra-page address is common to each logical intra-page address. Therefore, an intra-page address is not an object of address translation.
In a conventional memory access system, a real address is generated by combining a translated address portion and a non-translated address portion upon completion of address translation. More specifically, in an architecture employing the paging system, after a logical page address in a logical address is translated by an address translator into a real page address, the real page address is combined with an intra-page address, and the resultant address is transmitted to a memory as a real address. In other words, even if the intra-page address is established prior to address translation, processing of the intra-page address is started only upon completion of address translation of the page address, thus posing a problem. If page and intra-page addresses are divisionally transmitted to a main memory, both the addresses must be time-divisionally transmitted by using one address line, or address lines must be exclusively arranged for the addresses. However, since address translation normally requires one machine cycle, an extra machine cycle is required in time-divisional transmission, and hence degradation in performance is inevitably caused.
On the other hand, with an improvement in LSI technology, demands have surfaced for higher processing speed and reliability, and high-integration, high-density mounting of elements has been developed. As a result, one LSI chip or one mounting card requires a great number of input/output signal lines. Therefore, a decrease in number of input/output signal lines is indispensable for high-integration, high-density mounting.